Job overview
- Location
- Austin, Texas, United States
- Job type
- Full-time
- Work mode
- On-site
- Salary
- Not disclosed
- Category
- Engineering
- Posted
- Valid through
At a glance by CareerCola
- Company
- Cadence
- Role
- Lead Design Engineer
- Location
- Austin, Texas, United States
- Employment type
- Full-time
- Work mode
- On-site
- Category
- Engineering
- Posted
- 6 Oct 2026
- Valid through
- 5 Nov 2026
About the role
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Core Responsibilities
- Strategy and Architecture
Verification Planning: Define the overall verification strategy, including the choice of methodology (typically UVM/SystemVerilog), tools, and infrastructure.
Testbench Architecture: Design scalable, reusable, and robust verification environments. This includes developing Bus Functional Models (BFMs), monitors, scoreboards, and checkers.
Feature Extraction: Analyze architectural specifications to identify critical features and corner cases that require rigorous testing.
- Execution and Technical Leadership
Development: Write complex test cases and sequences to achieve high functional coverage.
Debug: Lead the root-cause analysis of complex design bugs, collaborating closely with design engineers to implement fixes.
Constraint Random Testing: Implement constrained-random stimulus generation to explore the design space beyond directed tests.
Formal Verification: Utilize formal tools to prove specific properties or find deep-seated bugs that simulation might miss.
- Metric Management
Coverage Analysis: Monitor and analyze functional and code coverage metrics.
Gate-Level Simulation (GLS): Oversee simulations on the synthesized netlist to verify timing and reset behavior.
Sign-off: Define the "definition of done" and provide final technical approval for the verification phase.
- Soft Skills and Leadership
Mentorship: Guiding junior engineers on coding standards and debugging techniques.
Cross-functional Collaboration: Acting as the primary technical point of contact between the design, architecture, and emulation teams.
Project Management: Managing timelines, identifying risks in the verification schedule, and prioritizing tasks to meet project deadlines.
Required Qualifications
B.E./B.Tech or M.Tech/M.S. in Electronics, VLSI, or related field
4–7 years of hands-on DV experience in semiconductor/ASIC/SoC companies
We’re doing work that matters. Help us solve what others can’t.
About Cadence
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