Stay safe: CareerCola does not guarantee employer authenticity. Never pay fees or share OTP, bank details, or passwords to obtain a job. Job Safety policy · Report this job

Staff Verification Design Engineer

Semtech

  • Location Hyderabad, Telangana, India
  • Job type Full-time
  • Work mode On-site
  • Salary Not disclosed
  • Posted

Job overview

Location
Hyderabad, Telangana, India
Job type
Full-time
Work mode
On-site
Salary
Not disclosed
Category
IT & Technology
Posted
Valid through

At a glance by CareerCola

Company
Semtech
Role
Staff Verification Design Engineer
Location
Hyderabad, Telangana, India
Employment type
Full-time
Work mode
On-site
Category
IT & Technology
Posted
7 Nov 2026
Valid through
7 Dec 2026

About the role

Responsibilities:

  • Perform block and chip-level verification in register-transfer level (RTL), gate-level and analog/mixed-signal (AMS).
  • Run digital/mixed-signal simulations as well as formal verification.
  • Work closely with the design team to create verification strategy and detailed verification plan.
  • Develop tests, run regressions and monitor coverage to ensure tape-out quality.
  • Participate in design or project reviews and support these with verification perspective and schedule/priority assessment.
  • Support post-silicon bring-up and debug, for bench validation as well as automated test equipment (ATE) testing.
  • Improve verification scalability and portability from project to project by environment enhancement and tools automation.

Minimum Qualifications:

  • 3+ years experience in semiconductor industry
  • M.S. in EE/CS/CE or higher
  • Hands-on experience with System Verilog as High-level Verification Language and UVM implementation.
  • Debugging digital simulation in both RTL and gate-level netlist, isolating issues in both module and system level.
  • Scripting experience in Python or Perl.
  • Clear understanding of ASIC design flow
  • Solid analytical, synthesis and problem-solving skills
  • Independent, self-motivated, rigorous, team player and able to follow through
  • Excellent verbal and written communication skills

Desired Qualifications

  • Experience of setting up UVM verification environment from scratch
  • Familiarity with VHDL or System Verilog RNM
  • Automation of verification flow with Python/Perl in industrial setting
  • Analog behavioral model development/verification experience

#LI-Onsite

About Semtech

Learn more about Semtech on their company profile.

View company profile

Reading that matches this role.

All guides